Definition
Wafer-level electrical test measures process structures and die through temporary probe contact to monitor fabrication, classify die, and avoid packaging clearly failing units.
Process position
Inputs
- Completed wafer
- Test program and limits
- Probe card and tester interface
- Wafer map and product genealogy
Outputs
- Parametric and functional results
- Die bin map
- Known-good-die candidates
- Yield signatures
How it works
- 01Align wafer and probe interface
- 02Contact process-monitor or die pads
- 03Apply electrical stimuli and measure response
- 04Control temperature where required
- 05Assign bins and record coordinates
- 06Review yield and release wafer
Process control profile
Materials, equipment, defects, and metrology
These records connect a physical input and tool module to its failure mechanism, detection method, and release decision. They complement the broader inventories in the control surface.
Material focus
Probe interface, reference material, test program, and limit set
Creates temporary electrical contact and defines stimuli, measurements, bins, and disposition logic.
Control: Control probe wear, contamination, planarity, program revision, limits, correlation, and coordinate mapping.
Failure link: Contact or data errors can falsely reject good die or pass bad die into expensive assembly.
Equipment module
ATE, wafer prober, probe card, thermal chuck, and data system
Contacts die, applies patterns and conditions, records results, and preserves wafer-map identity.
Control variables: Contact force, touchdown, temperature, timing, voltage/current accuracy, parallelism, and retest policy.
Integration risk: Test cell, probe interface, reference wafer, and data pipeline must be correlated as one system.
Defect mechanism
Contact false fail, test escape, or map error
Poor contact, limited coverage, thermal drift, program error, or coordinate mismatch corrupts die classification.
Detection: Contact diagnostics, reference correlation, yield maps, bin signatures, and downstream test correlation.
Downstream effect: Wastes good die, assembles bad die, or loses traceability between wafer and package.
Metrology gate
Electrical wafer probe and spatial yield analysis
Measures device parameters and function at known wafer coordinates.
Release decision: Determines die bins and wafer or lot disposition before singulation and assembly.
Limitation: Passing wafer test cannot observe every package-induced or lifetime failure mechanism.
Wafer test serves both process and product decisions
Process-monitor structures reveal whether fabrication met electrical targets; die-level tests classify individual circuits before the wafer is cut. The resulting spatial patterns can also point back to equipment, patterning, or contamination mechanisms.
Known-good die is a probability, not an absolute
Wafer sort is constrained by contact, time, temperature, coverage, and observability. A passing die is a qualified candidate for assembly under a defined test flow, not proof that every latent defect or later package interaction has been eliminated.
Sources
Citations support the tagged claims above. Access dates record when Maha Strategies last checked the public source.
- [1]Technical Briefing: Semiconductor Test · Advantest · 2024 · accessed 2026-08-13
- [2]Test Services · ASE · accessed 2026-08-13
- [3]IC Semiconductor Test Services · Amkor Technology · accessed 2026-08-13
Public capability landscape
Supplier profiles
Named companies are research leads based on public evidence. Inclusion does not establish customer qualification, process-of-record status, available capacity, or supplier ranking.
Semiconductor automatic test equipment
Advantest
Supplies semiconductor test systems and interfaces used at wafer sort, final test, and other screening stages.
Evidence profile →
Outsourced semiconductor assembly and test
ASE Technology
Provides semiconductor assembly, packaging, wafer probe, final test, and related engineering services.
Evidence profile →
Outsourced semiconductor assembly and test
Amkor Technology
Provides package design, wafer preparation, die attach, wire bond, flip chip, stacked-die assembly, and semiconductor test services.
Evidence profile →
Process control, inspection, and metrology
KLA
Supplies inspection, metrology, review, and yield-analysis systems across reticles, wafers, and packaging.
Evidence profile →