[ Technical knowledge graph // v0.1 ]
Understand the machinery beneath the brief.
Knowledge decomposes complex industries into processes, materials, equipment, controls, and failure modes. Every technical claim carries a citation or an explicit analytical boundary; every article links back to the Intelligence decisions it supports.
Explore the complete 89-node semiconductor process map →25 published nodes
8 lifecycle stages
Claim-level evidence status
Bidirectional Intelligence links
Taxonomy
Domain · 1
A system-level map that joins processes, materials, equipment, and decisions.
Process · 18
A manufacturing operation with defined inputs, controls, outputs, and failure modes.
Material · 1
A material family described by function, grade, process exposure, and qualification evidence.
Equipment · 0
A tool class described by process role, control variables, and production constraints.
Concept · 5
A cross-cutting technical idea used across multiple processes or product architectures.
Design
Architecture, logic design, verification, physical implementation, and tape-out.
Semiconductor manufacturing
A system map of semiconductor design, wafer fabrication, interconnect formation, test, assembly, packaging, and reliability qualification.
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IC design to tape-out
How requirements become architecture, verified logic, physical layout, signoff evidence, and the released database used to make masks.
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Masks and reticles
How signed-off chip layout is corrected, fractured, written, processed, inspected, repaired, and qualified as a lithography reticle set.
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RTL to physical design
The core digital implementation flow from behavioral hardware description to placed, routed, extracted, and signed-off geometry.
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Yield learning & SPC
How measurements, defect maps, equipment history, electrical test, and controlled experiments become process corrections and design feedback.
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Wafer preparation
Crystal growth, slicing, lapping, polishing, cleaning, and incoming-wafer qualification.
Cleanrooms & fab utilities
Why airflow, ultrapure water, gases, vacuum, chemicals, temperature, vibration, and material discipline are part of the semiconductor process.
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Metrology & inspection
How fabs measure dimensions, overlay, films, composition, defects, and electrical behavior without confusing measurement with process control.
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Silicon wafer preparation
How electronic-grade silicon becomes a flat, polished, oriented, and qualified substrate for device fabrication.
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Wafer cleaning
How wet, vapor, plasma, and brush cleans remove particles, organics, metals, polymers, oxides, and residues between critical process steps.
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FEOL
Formation of active devices in and on the semiconductor substrate.
Ion implantation & annealing
How ion dose, energy, angle, masking, lattice damage, and thermal activation create electrically active semiconductor regions.
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Photolithography
How coating, alignment, exposure, baking, development, masks, optics, and process control create patterned resist for semiconductor fabrication.
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Plasma etch
How wet, dry, plasma, selective, and atomic-layer etch remove material while controlling depth, profile, selectivity, damage, and residues.
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Thermal processing
How controlled temperature and atmosphere grow oxide, diffuse species, anneal films, drive reactions, and stabilize wafer structures.
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Thin-film deposition
How semiconductor fabs create conductive, insulating, barrier, liner, and functional films using PVD, CVD, ALD, and related methods.
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MEOL
Contacts and local interconnects that connect transistors to the wiring stack.
BEOL
Multilevel metal and dielectric wiring that connects devices into circuits.
Wafer test
Electrical screening, defect learning, wafer sort, thinning, and singulation preparation.
Advanced packaging
How substrates, RDL, interposers, TSVs, fan-out, chiplets, memory stacks, assembly, test, and thermal design become one system.
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Wafer sort
How process-monitor structures and individual die are electrically probed before assembly, generating parametric evidence and known-good-die candidates.
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Thinning & dicing
How finished wafers are protected, back-ground, stress-relieved, singulated, inspected, picked, and transferred without damaging thin die.
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Assembly & packaging
Die interconnection, protection, system integration, thermal paths, and package formation.
Direct-to-silicon cooling
How backside microchannels, manifolds, seals, coolants, flow control, inspection, and serviceability change AI-chip thermal management.
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Substrates & RDL
How organic substrates, interposers, and redistribution layers fan dense die connections into package-scale power, signal, and board interfaces.
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Underfill & encapsulation
How polymeric materials fill interconnect gaps, redistribute stress, protect die and wires, and become a permanent part of package reliability.
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Wire bond & flip chip
How die are attached and electrically connected by fine wires or area-array bumps, and why each architecture creates different process windows.
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Final test & reliability
Package test, system-level test, qualification, failure analysis, and field feedback.
Final test & burn-in
How packaged devices are screened, characterized, binned, stressed, and exercised in increasingly system-like conditions before shipment.
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Reliability & failure analysis
How products are stressed, monitored, statistically interpreted, dissected, and improved before release and after field failures.
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