ProcessStatus: FOUNDATIONALUpdated 2026-08-13

Package Substrates and Redistribution Layers

How organic substrates, interposers, and redistribution layers fan dense die connections into package-scale power, signal, and board interfaces.

Definition

Package substrates and redistribution layers provide patterned conductors, dielectrics, vias, pads, and mechanical support that transform the die-level interconnect pitch and route signals and power through a package.

Process position

Inputs

  • Package electrical and mechanical design
  • Core or carrier
  • Conductive and dielectric materials
  • Known-good die and assembly rules

Outputs

  • Qualified substrate, interposer, or RDL structure
  • Electrical continuity and dimensional records

How it works

  1. 01Build or prepare the carrier
  2. 02Form dielectric and via layers
  3. 03Pattern and plate redistribution metal
  4. 04Create pads and surface finish
  5. 05Inspect and electrically test
  6. 06Attach die or singulate the structure

Process control profile

Materials, equipment, defects, and metrology

These records connect a physical input and tool module to its failure mechanism, detection method, and release decision. They complement the broader inventories in the control surface.

Material focus

Copper, build-up dielectric, core or carrier, vias, finish, and solder mask

Redistribute fine die connections into package-scale signal, power, ground, and board interfaces.

Control: Control dielectric thickness, copper properties, adhesion, surface finish, moisture, particles, and warpage.

Failure link: Material or interface variation changes impedance, registration, jointability, and package mechanics.

Equipment module

Lamination/coating, lithography, plating, via formation, inspection, and electrical test line

Builds repeated dielectric, via, and conductor layers and qualifies each substrate site.

Control variables: Registration, line/space, via geometry, plating, lamination, cure, planarity, and warpage.

Integration risk: Substrate design, die bump map, assembly flow, and test access must close together.

Defect mechanism

Open, short, via void, misregistration, or delamination

Patterning, plating, via formation, cure, contamination, or stress damages routing or interfaces.

Detection: AOI, X-ray, continuity, impedance, warpage, coplanarity, and cross-section.

Downstream effect: Causes package yield loss, signal or power-integrity failure, or thermo-mechanical fatigue.

Metrology gate

Substrate geometry and electrical test

Measures line/via integrity, dimensional registration, flatness, continuity, and impedance.

Release decision: Identifies known-good sites before valuable die are attached.

Limitation: Electrical tests may not expose marginal adhesion or latent thermo-mechanical weakness.

The package is a geometric transformer

Fine die bumps cannot generally connect directly to a board-scale interface. RDL, interposers, and substrates redistribute that pitch while also carrying return paths, power delivery, mechanical loads, and heat.

Source-supported[1][2]

Advanced packages use redistribution and interconnect structures to integrate multiple components and connect them at package scale.

Known-good sites protect expensive die

When die are attached to a prebuilt RDL or substrate, inspection and electrical test of that structure can prevent valuable die from being placed on known-defective sites. That changes the economic value of upstream substrate yield.

Source-supported[2]

RDL structures can be inspected before die attach so costly die are placed only on known-good sites.

Sources

Citations support the tagged claims above. Access dates record when Maha Strategies last checked the public source.

  1. [1]3DFabric: 3D Silicon Stacking and Advanced Packaging · TSMC · accessed 2026-08-13
  2. [2]A New RDL-First PoP Fan-Out Wafer-Level Package Process · Amkor Technology · 2020 · accessed 2026-08-13

Public capability landscape

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