Contamination control
Control particles, metals, ions, organics, moisture, electrostatic discharge, and cross-contamination through facilities, carriers, garments, cleans, and material specifications.
Wafer preparation through final packing
[ Design → wafer → package → field ]
Complete Semiconductor Manufacturing Process Map
A product-neutral map of the full manufacturing system—from requirements and RTL through masks, transistor formation, multilayer wiring, wafer sort, heterogeneous assembly, final test, qualification, and production feedback.
10 phases89 process nodes8 continuous controlsUpdated 2026-08-13
System view
The primary value stream
Forward arrows carry a progressively more valuable physical or digital product. Feedback returns yield, reliability, and field evidence upstream.
- 01
Product definition & architecture
6 nodes
- 02
Circuit design, verification & tape-out
10 nodes
- 03
Mask data preparation & reticle fabrication
6 nodes
- 04
Starting wafer manufacture & incoming qualification
9 nodes
- 05
FEOL — transistor formation
11 nodes
- 06
MEOL — contacts & local interconnect
8 nodes
- 07
BEOL — multilayer interconnect
12 nodes
- 08
Wafer acceptance, probe & die preparation
8 nodes
- 09
Assembly & packaging
10 nodes
- 10
Final test, qualification & production feedback
9 nodes
← Failure analysis, yield learning, reliability, and field feedback close the loop to design and process control ←
DesignMaskSubstratePatternFilmModifyInterconnectTestAssemblyControl↻ repeated or iterative
01
Product definition & architecture
Translate a market or system requirement into a feasible silicon, package, software, cost, and test architecture.
Inputs
- · Workloads and use cases
- · Power, performance, area, cost, schedule, safety, and security requirements
- · Process-node and supply options
Outputs
- · Product requirements
- · System and chip architecture
- · Make/buy/IP plan
- · Initial package, test, and manufacturing assumptions
- Design1.1
Requirements capture
Define functions, interfaces, operating conditions, lifetime, regulatory obligations, and economic targets.
Technical article → - Design1.2
Workload modeling
Model representative software, data movement, latency, throughput, memory, and power behavior.
- Design1.3
Architecture exploration
Compare compute, memory, interconnect, accelerator, analog, RF, and chiplet partitions.
- Design1.4
Technology selection
Select process nodes, device options, memories, IP, package class, and thermal approach.
- Design1.5
PPA, yield & cost model
Establish power-performance-area budgets and connect die size, expected yield, package, and test cost.
- Test1.6
Verification & test strategy
Define pre-silicon verification, DFT, manufacturing test, qualification, and observability before implementation.
Release gate
Architecture review confirms feasible requirements, interfaces, budgets, technology availability, and verification coverage.
Feedback may return to: Product definition & architecture
02
Circuit design, verification & tape-out
Convert the architecture into a verified, physically manufacturable layout and production test content.
Inputs
- · Approved architecture
- · Process design kit
- · Standard cells, memories, analog/RF blocks, and licensed IP
- · Package and test constraints
Outputs
- · Signed-off layout database
- · Manufacturing test patterns
- · Mask data
- · Bring-up and characterization plan
- Design2.1
Microarchitecture
Define pipelines, state machines, data paths, clocking, power domains, memories, and interfaces.
- Design2.2
RTL & custom circuit design
Implement digital logic and design custom analog, RF, memory, I/O, and physical IP.
Technical article → - Design2.3 ↻
Functional verification
Use simulation, formal methods, emulation, prototypes, coverage, and hardware/software co-verification.
Technical article → - Test2.4
DFT & ATPG
Insert scan, memory self-test, boundary test, debug, and other structures; generate production patterns.
- Design2.5
Logic synthesis
Map RTL into technology cells under timing, power, area, test, and physical constraints.
Technical article → - Design2.6
Floorplan & power network
Place major blocks, I/O, macros, clock and power structures, and package connection assumptions.
- Design2.7 ↻
Place, clock & route
Place cells, build clock networks, route signals, and optimize congestion, timing, power, and integrity.
Technical article → - Control2.8 ↻
Extraction & signoff analysis
Close timing, power, IR drop, electromigration, signal integrity, thermal, and variation requirements.
Technical article → - Control2.9 ↻
Physical verification
Run design-rule, layout-versus-schematic, electrical-rule, density, antenna, and manufacturability checks.
Technical article → - Design2.10
Tape-out
Freeze the released layout, checksums, revisions, test content, and manufacturing handoff package.
Technical article →
Release gate
All signoff views, physical checks, IP revisions, waivers, test coverage, and tape-out configuration are approved.
Feedback may return to: Product definition & architecture · Circuit design, verification & tape-out
03
Mask data preparation & reticle fabrication
Turn signed-off layout polygons into inspected reticles that can print each process layer.
Inputs
- · Released layout database
- · Layer map and process bias rules
- · Scanner and illumination assumptions
Outputs
- · Qualified reticle set
- · Inspection and repair records
- · Pellicle and mask logistics record
- Mask3.1
Mask data preparation
Fracture layout, apply process bias, dummy features, optical/proximity corrections, and computational patterning.
Technical article → - Mask3.2
Mask writing
Expose the reticle blank with an electron-beam writer and tightly controlled data path.
Technical article → - Mask3.3
Develop, etch & clean
Develop the mask resist, transfer the pattern into absorber material, strip, and clean.
- Control3.4
CD & registration metrology
Measure feature size, placement, uniformity, and pattern fidelity.
- Control3.5 ↻
Inspection & repair
Find printable defects, repair where allowed, and reinspect repaired regions.
Technical article → - Mask3.6
Pellicle, qualification & release
Protect the patterned surface where applicable and release the reticle into controlled fab logistics.
Release gate
Reticle critical dimensions, registration, defect disposition, revision identity, and scanner compatibility are accepted.
Feedback may return to: Circuit design, verification & tape-out · Mask data preparation & reticle fabrication
04
Starting wafer manufacture & incoming qualification
Produce a clean, flat, crystallographically controlled substrate suitable for device fabrication.
Inputs
- · Electronic-grade silicon or compound-semiconductor feedstock
- · Dopant specification
- · Crystal and wafer geometry specification
Outputs
- · Qualified bare or epitaxial wafers
- · Crystal, surface, contamination, and geometry records
- Substrate4.1
Feedstock purification
Produce electronic-grade semiconductor feedstock with controlled impurities.
- Substrate4.2
Single-crystal growth
Grow an oriented ingot while controlling dopant, resistivity, oxygen, defects, and diameter.
Technical article → - Substrate4.3
Ingot conditioning
Crop, grind, orient, and mark the crystal before wafering.
- Substrate4.4
Wafer slicing
Slice the ingot into wafers with controlled thickness and kerf damage.
Technical article → - Substrate4.5
Edge, lap & damage removal
Shape edges, flatten surfaces, and remove mechanically damaged material.
- Substrate4.6
Chemical-mechanical polish
Create the low-roughness, high-flatness device surface.
Technical article → - Substrate4.7
Final clean
Remove particles, metals, organics, and native residues to the incoming specification.
Technical article → - Film4.8
Epitaxy or engineered substrate
Optionally grow a controlled epitaxial layer or create SOI and other engineered starting structures.
Technical article → - Control4.9
Incoming qualification
Verify flatness, thickness, resistivity, crystal defects, surface condition, particles, and traceability.
Release gate
Starting wafer meets geometry, crystal, electrical, surface, defect, contamination, and traceability specifications.
Feedback may return to: Starting wafer manufacture & incoming qualification
05
FEOL — transistor formation
Create electrically isolated, controlled transistor structures in and on the wafer substrate.
Inputs
- · Qualified starting wafer
- · Reticles
- · Process gases, precursors, resists, wet chemicals, dopants, and films
Outputs
- · Wafer with completed active devices
- · Inline physical and electrical process-control data
- Modify5.1 ↻
Surface clean & preparation
Condition the wafer surface and remove contamination before each sensitive module.
Technical article → - Modify5.2
Wells & channel engineering
Pattern and introduce dopants that establish body regions, thresholds, isolation, and punch-through control.
Technical article → - Pattern5.3
Device isolation
Pattern, etch, fill, and planarize isolation structures between active regions.
Technical article → - Film5.4
Channel and epitaxial structures
Grow or deposit channel, stressor, sacrificial, or selective epitaxial materials where required.
Technical article → - Film5.5
Gate dielectric & electrode stack
Form interfacial layers, high-k dielectric, work-function metals, and gate conductors.
Technical article → - Pattern5.6
Gate patterning
Print and transfer the gate or replacement-gate geometry with critical profile control.
Technical article → - Pattern5.7
Spacer formation
Deposit and anisotropically etch sidewall spacers that control later implants and source/drain geometry.
Technical article → - Modify5.8
Source/drain formation
Introduce extensions and deep junctions or grow raised source/drain structures.
Technical article → - Modify5.9
Activation & thermal processing
Repair lattice damage, activate dopants, form interfaces, and manage diffusion within the thermal budget.
Technical article → - Film5.10
Contact resistance reduction
Form low-resistance semiconductor/metal compounds on exposed contact regions where the integration uses them.
- Control5.11 ↻
Inline metrology & electrical monitors
Measure CDs, overlay, profiles, films, defects, sheet resistance, and device test structures after critical modules.
Technical article →
Release gate
Transistor geometry, electrical parameters, defectivity, reliability monitors, and excursion dispositions meet the device-module specification.
Feedback may return to: Mask data preparation & reticle fabrication · FEOL — transistor formation
06
MEOL — contacts & local interconnect
Connect transistor terminals to a dense, low-resistance local wiring system.
Inputs
- · Completed transistor wafer
- · Contact masks
- · Dielectrics, liners, barriers, and conductive fill materials
Outputs
- · Completed contacts and local interconnect
- · Contact-resistance, profile, defect, and continuity data
- Film6.1
Contact dielectric deposition
Deposit and cure the dielectric that isolates devices from local wiring.
Technical article → - Pattern6.2
Contact lithography
Define contact openings to gates and source/drain regions.
Technical article → - Pattern6.3
Contact etch & clean
Etch high-aspect-ratio openings, stop at the target interface, and remove residues without excess damage.
Technical article → - Film6.4
Interface, liner & barrier
Prepare exposed surfaces and deposit adhesion, diffusion-control, or nucleation layers.
Technical article → - Interconnect6.5
Contact fill
Fill contacts with tungsten, cobalt, ruthenium, or another integration-specific conductor.
- Interconnect6.6
Planarization & clean
Remove overburden, restore planarity, and clean particles and residues.
Technical article → - Interconnect6.7
Local interconnect formation
Pattern and form the first dense connections between devices and the global metal stack.
- Control6.8 ↻
Contact metrology & electrical control
Monitor contact dimensions, voids, resistance distributions, opens, shorts, and contamination.
Release gate
Contact resistance, continuity, defectivity, topography, and reliability structures meet release limits.
Feedback may return to: FEOL — transistor formation · MEOL — contacts & local interconnect
07
BEOL — multilayer interconnect
Build the repeated dielectric, via, and metal hierarchy that connects devices into a working circuit.
Inputs
- · Contacted wafer
- · Interconnect reticles
- · Low-k dielectrics, hard masks, liners, barriers, metals, plating chemistry, and CMP consumables
Outputs
- · Completed multilayer wiring stack
- · Top-level pads or bond structures
- · Interconnect electrical and defect data
- Film7.1 ↻
Interlayer dielectric
Deposit, cure, and condition the dielectric for the next wiring level.
Technical article → - Film7.2 ↻
Hard-mask stack
Build cap, stop, hard-mask, antireflective, and patterning layers as required.
Technical article → - Pattern7.3 ↻
Via/trench lithography
Print single- or multi-patterned openings for vias and lines.
Technical article → - Pattern7.4 ↻
Via/trench etch
Transfer line and via geometry through dielectric stacks with profile and stop-layer control.
Technical article → - Modify7.5 ↻
Post-etch clean
Remove polymers, residues, and exposed-interface contamination before metallization.
Technical article → - Film7.6 ↻
Barrier, liner & seed
Prepare interfaces and deposit layers that enable fill, adhesion, nucleation, and diffusion control.
Technical article → - Interconnect7.7 ↻
Metal fill
Fill patterned features using copper plating, CVD, PVD, ALD, reflow, or another node-specific scheme.
Technical article → - Modify7.8 ↻
Metal anneal
Stabilize grain structure, interfaces, stress, or electrical properties where required.
- Interconnect7.9 ↻
CMP & post-CMP clean
Remove overburden, control dishing and erosion, restore planarity, and clean the surface.
Technical article → - Interconnect7.10 ↻
Repeat wiring levels
Repeat the dielectric-to-CMP module for local, intermediate, global, and thick top-metal levels.
Technical article → - Film7.11
Passivation & pad opening
Protect the completed wafer and expose pads or prepare top-level redistribution and bump interfaces.
- Control7.12 ↻
Inline inspection & electrical control
Track overlay, profiles, film properties, defects, resistance, capacitance, opens, shorts, and reliability monitors.
Release gate
All metal levels meet resistance, capacitance, continuity, defect, electromigration, dielectric, planarity, and outgoing-wafer criteria.
Feedback may return to: Mask data preparation & reticle fabrication · MEOL — contacts & local interconnect · BEOL — multilayer interconnect
08
Wafer acceptance, probe & die preparation
Measure wafer and die performance, preserve traceability, and prepare selected die for assembly.
Inputs
- · Completed wafer
- · Test programs, probe cards, limits, and product configuration
- · Assembly route and wafer map requirements
Outputs
- · Wafer-acceptance disposition
- · Die-level bin map and known-good-die candidates
- · Thinned, bumped, diced, or framed die/wafer
- Test8.1
Wafer acceptance test
Measure process-control structures and electrical parameters that characterize the completed wafer process.
Technical article → - Control8.2
Outgoing wafer inspection
Inspect edge, backside, surface, passivation, pads, and gross defects before or around probe.
- Test8.3
Probe correlation & release
Correlate tester, probe card, temperature, limits, and reference material before production testing.
- Test8.4
Wafer probe / sort
Contact each die, execute structural and functional tests, assign bins, and preserve the wafer map.
Technical article → - Control8.5 ↻
Yield analysis & disposition
Separate systematic from random loss, contain excursions, and decide wafer, lot, or die disposition.
Technical article → - Assembly8.6
Bumping or wafer-level RDL
Optionally form redistribution and die/package interconnect structures before singulation.
Technical article → - Assembly8.7
Backgrind & thinning
Thin the wafer to package requirements while controlling stress, damage, contamination, and handling.
Technical article → - Assembly8.8
Dicing or stealth singulation
Separate die, inspect them, and maintain identity between wafer coordinates and physical units.
Technical article →
Release gate
Accepted die meet bin, traceability, physical-integrity, contamination, thickness, and assembly-input requirements.
Feedback may return to: Circuit design, verification & tape-out · FEOL — transistor formation · MEOL — contacts & local interconnect · BEOL — multilayer interconnect · Wafer acceptance, probe & die preparation
09
Assembly & packaging
Create reliable electrical, thermal, and mechanical connections between selected die and the external system.
Inputs
- · Accepted die or wafers
- · Package substrate, leadframe, interposer, RDL, or carrier
- · Interconnect, encapsulation, and thermal materials
Outputs
- · Marked and traceable packaged devices
- · Assembly inspection and process-control data
- Control9.1
Incoming inspection & kitting
Verify die maps, substrates, materials, revisions, moisture status, shelf life, and traceability.
- Assembly9.2
Die placement & bonding
Attach die by adhesive, solder, thermocompression, hybrid bond, or another architecture-specific method.
Technical article → - Assembly9.3
Companion die & memory integration
Place and connect chiplets, HBM, bridges, interposers, passives, or optical components where used.
Technical article → - Assembly9.4
Electrical interconnect
Create wire bonds, flip-chip joints, microbumps, copper bonds, TSV/RDL paths, or leadframe connections.
Technical article → - Assembly9.5
Underfill, mold & cure
Reinforce or encapsulate sensitive structures while controlling voids, stress, flow, and contamination.
Technical article → - Assembly9.6
Substrate or board-side termination
Attach balls, leads, columns, lands, or other external connections and finish exposed surfaces.
- Assembly9.7
Lid, TIM & cooling interface
Build the heat path using lids, heat spreaders, TIMs, cold plates, or direct liquid structures.
Technical article → - Assembly9.8
Package singulation & finish
Separate molded strips or panels, mark units, clean, and prepare them for electrical test.
- Control9.9 ↻
Assembly inspection
Use optical, X-ray, acoustic, coplanarity, warpage, and traceability checks at risk-appropriate insertions.
- Test9.10 ↻
Intermediate test
Test between value-adding assembly steps when the architecture and economics justify early screening.
Release gate
Package passes workmanship, connectivity, warpage, delamination, void, thermal-interface, marking, and traceability criteria.
Feedback may return to: Circuit design, verification & tape-out · Wafer acceptance, probe & die preparation · Assembly & packaging
10
Final test, qualification & production feedback
Demonstrate shipped-unit function and establish that the product, package, and manufacturing flow meet intended-use reliability requirements.
Inputs
- · Assembled units
- · Test programs, load boards, sockets, handlers, and system fixtures
- · Qualification plan and mission profile
Outputs
- · Shippable tested units
- · Characterization and qualification evidence
- · Yield, failure-analysis, and field-learning feedback
- Test10.1
Final ATE test
Test digital, memory, analog, RF, mixed-signal, power, and interface functions across specified conditions.
Technical article → - Test10.2
Parametric binning
Classify units by functional, speed, power, leakage, voltage, or application-specific limits.
- Test10.3
Burn-in or stress screen
Apply product-specific stress where justified to detect early-life or latent defects.
Technical article → - Test10.4
System-level test
Exercise selected units or production populations in a closer-to-use hardware and software environment.
Technical article → - Control10.5
Product & package qualification
Run environmental, mechanical, electrical, package, and lifetime stresses against the intended mission profile.
Technical article → - Control10.6 ↻
Failure analysis
Localize, expose, identify, and verify root causes using electrical, physical, chemical, and materials methods.
Technical article → - Control10.7 ↻
Corrective action & requalification
Contain affected material, correct the cause, verify effectiveness, and requalify when required.
- Control10.8
Outgoing quality & packing
Complete visual and sampling gates, bake or dry-pack as required, label, serialize, and release.
- Control10.9 ↻
Field returns & lifecycle monitoring
Connect customer returns, telemetry, reliability monitors, and lot genealogy to design and process learning.
Release gate
Released units meet test limits, qualification requirements, outgoing quality controls, traceability, and change-management obligations.
Feedback may return to: Product definition & architecture · Circuit design, verification & tape-out · Wafer acceptance, probe & die preparation · Assembly & packaging · Final test, qualification & production feedback
Continuous control plane
The systems running across every phase
Advanced process control
Use recipe control, run-to-run adjustment, fault detection, tool matching, chamber qualification, statistical control, and excursion containment.
Every production operation
Metrology & inspection
Measure geometry, overlay, film properties, composition, defects, electrical parameters, package interfaces, and reliability indicators at risk-appropriate points.
Every release gate
Yield learning
Correlate spatial signatures, tool history, materials, process context, test bins, physical analysis, and design structures to identify root causes.
Design through field returns
Traceability & change control
Preserve revision, lot, wafer, die, tool, recipe, material, operator, test, assembly, and shipment genealogy; qualify intentional changes.
Supply receipt through shipped unit
Reliability engineering
Translate the mission profile into design rules, monitors, screens, accelerated stresses, models, qualification, and field surveillance.
Architecture through lifecycle monitoring
Facilities & EHS
Provide controlled power, gases, vacuum, ultrapure water, exhaust, abatement, chemical delivery, fire protection, and worker/environment safeguards.
All factories and laboratories
Cybersecurity & data integrity
Protect design IP, mask data, recipes, equipment interfaces, test content, genealogy, and release decisions from loss or manipulation.
Digital thread across all phases
Sources and method
The map normalizes public descriptions from design, equipment, foundry, assembly, and test organizations into one product-neutral sequence. Sources support the existence and role of process families; exact recipes, limits, cycle times, masks, and insertions remain product- and manufacturer-specific.
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