Working definition
Neuromorphic co-design jointly specifies the workload, model, training procedure, compiler, placement, routing, numeric representation, device behavior, runtime, and host interface. A result belongs to that complete stack. Porting can change accuracy, sparsity, timing, and energy, so an algorithm result cannot be silently relabeled as a hardware result or vice versa.
Mechanism
- Express application constraints and target metrics.
- Map model operations to substrate capabilities.
- Iterate using measured bottlenecks and errors.
Measurements
- Mapping utilization
- Accuracy after deployment
- Full-stack latency and energy
Reproducibility controls
- Version hardware, software, firmware, and analysis code.
- Declare dataset, preprocessing, random seeds, and measurement boundary.
- Report repeated runs, variation, exclusions, and failed trials.
Limits and failure modes
- Co-design can overfit one benchmark.
- Compiler and host versions affect results.
Mathematical connection
Formal structure without substrate erasure
Model-to-substrate mapping
Find mappings that respect memory, fan-in, routing, precision, and timing constraints.
Inputs
- Model graph
- Hardware limits
- Objective weights
Outputs
- Feasible placement
- Constraint violations
- Trade-off record
Limit: A feasible mapping does not establish useful accuracy, energy, robustness, or superiority to conventional hardware.
Technical and governance sources
- [1]Taking Neuromorphic Computing to the Next Level with Loihi 2 · Intel Labs
Establishes: An official description of the Loihi 2 research chip, its programmable neuron models, event-based communication, on-chip learning support, and the Lava software framework used to construct neuromorphic applications.
Boundary: This is a vendor technical brief about a research platform. Performance and efficiency results remain workload-, configuration-, measurement-boundary-, and comparison-dependent and do not establish equivalence to biological intelligence.
- [2]SpiNNaker2 Developer Portal and Hardware Documentation · SpiNNcloud Systems and SpiNNaker2 community
Establishes: Maintained technical documentation for a many-core, event-based neuromorphic platform, including chip topology, processing elements, communication, software interfaces, and supported computational workloads.
Boundary: Architecture documentation establishes available mechanisms, not universal speed, energy, learning, biological plausibility, or production readiness. Claims require a named board, software version, workload, and system boundary.
- [3]NeuroBench: Advancing Neuromorphic Computing Through Collaborative, Fair and Representative Benchmarking · National Institute of Standards and Technology
Establishes: A community framework separating algorithm and system tracks and defining task, correctness, efficiency, and reporting procedures intended to make neuromorphic results more comparable and reproducible.
Boundary: A benchmark ranks submitted systems on declared tasks and metrics. It does not prove general intelligence, biological equivalence, safety, usefulness outside the benchmark, or superiority under unreported host and data costs.